Exemplary embodiments relate to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device including a metal silicide layer formed by a silicidation process and a method of manufacturing the same.
With the increasing integration degree of semiconductor device, the width of conductive wires within semiconductor device and a space between the conductive wires become smaller. In reducing interference between conductive wires, where interference normally tends to increase with the space/width, air gaps may be formed between neighboring conductive wires. Further, in improving resistance of the conductive wire which varies according to a reduction in the width, a part of the conductive wire made be formed into a metal silicide layer by siliciding a part of a stack layer forming the conductive wires. Here, in using both the air gap formation process and the silicidation process, electrical properties of semiconductor device may be degraded during a polish process or a dry etch process which are performed in advance for the silicidation process.
Features of the silicidation process are described in more detail below by taking a process of forming the word lines of a NAND flash memory device as an example with reference to FIGS. 1A and 1B.
Referring to FIG. 1A, a tunnel insulation layer 13 and a conductive layer 15 for a floating gate are formed over the active regions of a semiconductor substrate 11, including isolation regions and the active regions. For reference, FIGS. 1A and 1B are the cross-sectional views taken along a direction parallel to the active region of the semiconductor substrate 11.
Next, a dielectric layer 17 and a polysilicon layer (that is, a first conductive layer 19 for a control gate) are sequentially stacked. Gate hard mask patterns 21 are formed over the first conductive layer 19. Each of the gate hard mask patterns 21 is formed as a line type structure elongated in a direction crossing the active regions in order to define regions where the word lines are formed.
Next, the first conductive layer 19, the dielectric layer 17, and the conductive layer 15 are etched by using the gate hard mask patterns 21 as an etch mask. Consequently, the first conductive layer 19, the dielectric layer 17, and the conductive layer 15 are patterned along the active regions, thereby forming a plurality of stack patterns MP spaced apart from one another along the active regions. Each of the stack patterns MP includes first control gates CG1 coupled in a direction crossing the active regions, floating gates FG spaced apart from one another in a direction crossing the active regions, and the dielectric layer 17 formed between each of the first control gates CG1 and each of the floating gates FG.
Next, cell junctions 11a are formed by implanting impurities into the semiconductor substrate 11 between the gate hard mask patterns 21.
An insulation layer 25 is formed on the entire structure in which the cell junctions 11a are formed. The insulation layer 25 may be a spacer layer for protecting the sidewalls of the stack patterns MP. If a space between the stack patterns MP is formed to be narrow in order to increase the integration degree of semiconductor device, an upper portion of the space between the stack patterns MP is covered by the insulation layer 25 before the entire space between the stack patterns MP is filled with the insulation layer 25. Accordingly, an air gap 23 is formed between the stack patterns MP.
Referring to FIG. 1B, in order to improve resistance of the first control gate CG1, a process of siliciding an upper portion of the first control gate CG1 is performed. In order to perform the silicidation process, a process of exposing the first conductive layer 19 (that is, the polysilicon layer) is performed in advance. Next, the following processes are performed: a process of forming a metal layer over the exposed first conductive layer 19, a process of forming a first metal silicide layer by performing a primary annealing process so that metal of the metal layer is diffused into the first conductive layer 19 (that is, the polysilicon layer), a process of removing the remaining metal layer after the primary annealing process, and the silicidation process including a secondary annealing process of changing the first metal silicide layer into a second metal silicide layer 27, which is more stable than the first metal silicide layer and having low resistance. The metal silicide layer 27 formed by the secondary annealing process becomes second control gates CG2.
The second control gates CG2 are formed by siliciding the upper portions of the first control gates CG1, thus becoming word lines.
The process of exposing the first conductive layer 19 may be performed using chemical mechanical polishing (CMP) process (that is, a polish process) or an etch-back process (that is, a dry etch process). However, if the first conductive layer 19 is exposed by the CMP process, scratches may be formed on a surface of the first conductive layer 19 or slurry used when the CMP process may remain within the opened air gaps 23. Further, if the first conductive layer 19 is exposed by the etch-back process, the insulation layer 25 remaining on the sidewalls of the stack patterns MP and at the bottom of the air gaps 23 may be lost. Further, a surface A of the semiconductor substrate is exposed because the insulation layer 25 remained in the air gaps 23 is lost by the etch-back process.
Here, a method of improving the polish process or the dry etch process is useful to prevent degradation of electrical properties of semiconductor device.